IMAGE PROCESSING and MULTIMEDIA LABORATORY (IPML)

The newly formed Image Processing and Multimedia group of DUTH currently consists of faculty members, graduate students and supporting technical personnel. Its members teach courses in the areas of Computer Networks, Data Compression, Digital Signal Processing, Digital Image Processing and Image Coding. Their current research interests are on image compression, pattern and optical character recognition, image communication, multimedia image data bases and digital signal processing. Recently they have published papers in the areas of Image processing and multimedia technologies.

They have been actively involved in the definition, design and implementation of the CCITT/ISO (JBIG, JPEG, MPEG etc.), standards for coding, storage and retrieval of images (color & bilevel), where they have six international patents. They are interested in the implementation of multimedia techniques either with fast software or with special purpose devices. They are also working towards the design and implementation of an experimental computer network (based on UNIX/NOVELL), which will be used for the storage and transmission of multimedia University Documents and Images.

The Image & Multimedia Laboratory of DUTH has recently invested over 30 kECU (from Stride - Hellas 8) to its multimedia and image processing infrastructure.

Prof. Christos Chamzas, the director of the IPML Lab., has extensive experience (10 years with AT&T Bell Laboratories, Visual Communications Research Laboratory) in digital signal processing, communication systems and image coding. He has been working on problems in the Submarine Lightwave Systems, adaptive echo cancelers, mobile phones and image data bases. He has design and implement a variety of special purpose communication boards for the above projects. Recently, he has been a major player in the definition, design and implementation of the CCITT/ISO (JBIG, JBEG, etc), standards for coding, storage and retrieval of images (color & bilevel). He is currently interested in the implementation of the above algorithms either with fast software or with VLSI design.


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